1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a buried gate, a storage node and a bit line and a method of manufacturing the same.
2. Related Art
A dynamic random access memory (DRAM) of a semiconductor device includes a plurality of unit cells comprised of a capacitor and a transistor. The capacitor is used to store data and the transistor is used to transfer data between the capacitor and a bit line in response to a control signal (a word line) using a semiconductor property in which electric conductivity changes according to environment. A transistor includes three parts: a gate, a source, and a drain. Charges move between the source and drain according to the control signal input to the gate. The charges move between the source and drain through a channel region using the semiconductor property.
When a conventional transistor is fabricated on a semiconductor substrate, the gate is formed on the semiconductor substrate. Then the source and drain are formed by implanting impurities into the semiconductor substrate, thereby forming the channel region between the source and drain below the gate. A transistor having such a horizontal channel region occupies a relatively large area in the semiconductor substrate. Thus, since a complicated semiconductor memory device includes a plurality of transistors therein, it is difficult to reduce a unit cell area using a horizontal channel structure.
When a unit cell area of the semiconductor memory device is reduced, the number of semiconductor memory devices per a wafer increases and productivity can be improved. Various methods of reducing a unit cell area of a semiconductor memory device have been suggested. One of the various methods includes using a transistor having a recessed gate, which is formed in a recess in the semiconductor substrate, to form a channel region along a curvature of the recess, instead of a planar gate transistor having a horizontal channel region. In addition, a transistor having a buried gate, which is formed to be buried within a recess in the semiconductor substrate, has also been studied.
In a buried gate structure, an isolation gate is used to form a bit line contact and a storage node contact in a line type. However, a device employing an isolation gate is disadvantageous in that a unit cell area and a leakage current are increased compared to a device employing a conventional trench type device isolation layer.
However, problems arise with a buried gate structure using a trench type device isolation layer because a contact hole is patterned in a hole type and an dry etching process is used when a bit line contact is patterned. As the contact hole pattern size becomes smaller, it becomes harder to pattern the contact hole precisely. If the contact hole is under-etched, the active region fails to be open.
To overcome these problems, a method of forming one storage node contact plug in two active regions by combining two storage node contact plugs and separating the resulting storage node contact plug by a bit line, thereby forming separated storage node contact plugs, has been suggested. However, when the method is used, a spacer between the storage node contact plug and the bit line is thin such that parasitic capacitance increases, thus reducing sensing ability. On the other hand, when a height of the bit line is lowered to prevent these problems, bit line resistance increases.